The present invention relates to an information recording technique using a ferromagnetic material, particularly to a magnetic memory device utilizing magnetic tunnel junction.
A magnetic random access memory (hereinafter, abbreviated as MRAM) is a type of a solid state memory that can rewrite, hold, and read out record information any time by utilizing a magnetization direction of the ferromagnetic material as an information recording medium. This MRAM records information by corresponding binary coded information xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d whether the magnetization direction of the ferromagnetic material is parallel to or anti-parallel to a reference direction.
Recording information is written by switching the magnetization direction of the ferromagnetic material of each cell by a magnetic field generated by supplying a current to a write line disposed in a cross stripe shape. The power consumption during storing is principally zero.
Stored information is read out by utilizing a phenomenon in which the electric resistance of a memory cell changes depending on a relative angle between the magnetization direction of the ferromagnetic material that configures cells and a direction of a sense current or depending on a relative angle of magnetization between a plurality of ferromagnetic layers, so called the magnetoresistance effect.
The MRAM has the following advantages in comparison with a conventional semiconductor memory.
(a) Completely non-volatile. 1015 or more endurance cycles are possible.
(b) Nondestructive readout is possible, and refresh operation is not required, thus making it possible to reduce a readout cycle.
(c) The durability against radiation is strong in comparison with a charge storage type memory cell.
The degree of integration per a unit area for the MRAM and the write and readout times are expected to be approximately equal to those of the DRAM. Therefore, it is further expected to apply the MRAM to an external memory device for a portable digital audio instrument, a wireless IC card, and a mobile personal computer (PC) by utilizing significant non-volatile characteristics.
In an MRAM having its recording capacity of 1 Mb that is currently discussed for practical use, a Giant Magnetoresistance (hereinafter, abbreviated as a GMR effect) is employed for reading out stored information. An example of such an MRAM cell using an element that indicates the GMR effect (hereinafter, abbreviated as the GMR element), is disclosed in IEEE Trans. Mag., 33,3289 (1997)).
A value of the GMR effect of the tri-layered film made of a non-coupling NiFe/Cu/Co is about 6% to 8%. For example, in the aforementioned MRAM cell using the PseudoSpin-Valve structure, the distribution of the magnetic direction during readout of recorded information is controlled, whereby the resistance change of 5% or more is effectively obtained. However, in general, the sheet resistance of the GMR element is about some tens xcexa9/xcexcm2. Therefore, even in the case where the sheet resistance of 100 xcexa9/xcexcm2 and the resistance change rate of 5% are assumed, the output signal relevant to a sense current of 10 mA is merely 5 mV. Currently, in a MOS type field effect transistor that is practically available for use, the value of a source/drain current Ids is proportional to a rate between a channel width W and a channel length L, and the value of Ids when W=3.3 xcexcm and L=1 xcexcm is about 0.1 mA. Therefore, the value of the sense current of 10 mA used here is very excessive relevant to a transistor with sub-micron dimensions.
In order to solve this problem, in the MRAM cell using the GMR element, there is employed a method of connecting a plurality of GMR elements in series, and then, configuring a data lie (for example, refer to IEEE Trans. Comp. Pac. Manu. Tech. pt. A, 17,373 (1994).). However, in the case where memory cells are connected in series, there is a disadvantage that the power consumption efficiency during readout is greatly lowered.
In order to solve these problems, there is proposed an attempt to apply a ferromagnetic tunnel effect (Tunnel Magnetoresistance: hereinafter, abbreviated as a TMR effect) instead of the GMR effect. An element indicating the TMR effect (hereinafter, abbreviated as the TMR element) is primarily composed of a tri-layered film made of a ferromagnetic layer 1, an insulating layer, and a ferromagnetic layer 2, and current tunnels through the insulating barrier. The tunnel resistance value changes in proportion to a cosine of a relative angle in magnetization of both of the ferromagnetic metal layer, and an maximum value is obtained in the case where one magnetization is antiparallel to another.
For example, in tunnel junction of NiFe/Co/Al2O3/Co/NiFe, the magnetoresistance ratio exceeding 25% in a low magnetic field of 500e or less is found out (for example, refer to IEEE Trans. Mag., 33,3553 (1997)). The cell resistance value of the TMR element is typically between 104 ohms and 106 xcexa9 per a junction area (xcexcm2). Therefore, assuming that the resistance value is 10 kxcexa9, and the magnetoresistance ratio is 25% in a cell of 1 xcexcm2, a cell readout signal of 25 mV is obtained in a sense current of 10 xcexcA.
In an MRAM cell array using the TMR element, a plurality of TMR elements are connected in parallel on a data line. The following detailed structures are adopted.
(1) A structure in which a selection semiconductor element is disposed in series at each TMR element;
(2) A structure in which a selection transistor is disposed for each data line where a plurality of TMR elements are connected in parallel; and
(3) A structure in which a plurality of TMR elements are disposed in matrix, and a selection transistor is disposed for each row data line or each column data line (for example, refer to J. Appl. Phys., 81,3758 (1997)).
Among these structures, the structure of (1) has the most excellent characteristics in an aspect of power consumption efficiency during cell output voltage readout.
However, in the MRAM cell array having the structure of (1), it is required to supply a current to a semiconductor element connected to the TMR element during readout. As a semiconductor element, there are employed: a MOS type transistor; a diode element using the transistor; and a diode element using pn junction or Schottky junction. Therefore, in the case where there occurs dispersion in characteristics of these semiconductor elements, noise caused by such dispersion cannot be ignored.
For example, in the case of a MOS transistor, a voltage drop between a source and a drain reaches 100 mV or more in a rule of 0.25 xcexcm. That is, if there exists a dispersion of 10% in characteristics of a semiconductor element, noise of 10 mV or more is generated by such dispersion. In addition, in consideration of a noise generated at a peripheral circuit such as noise coupled with data line or noise due to dispersion in characteristics of the sense amplifier, the noise level is greater than 10 mV. In a current cell output voltage of about 20 mV to 30 mV, an only signal-to-noise ratio of some decibels can be obtained.
In order to improve the signal-to-noise ratio, in a conventional MRAM cell array, there is often employed a method for comparing an output voltage V of a selected single memory cell with a reference VREF, thereby differentially amplifying a differential voltage Vsig therebetween. A first object of this is to eliminate noise generated in a data line pair to which a memory cell connects, and a second object of this is to eliminate an offset of a cell output voltage Vsig due to dispersion in characteristics of the semiconductor element for driving a sense line or selecting a cell. As a circuit for generating the reference voltage VREF, there are employed a circuit using the semiconductor element or dummy cell. However, in this method, the selected memory cell and the circuit for generating the reference voltage are connected to their respective cell selection semiconductor elements, making it impossible to completely eliminate an offset of the cell output voltage V due to dispersion in characteristics of the semiconductor element.
Further, in the prior art, in general, the reference voltage VREF is defined as an intermediate voltage between output voltages VF and VAF that correspond to cell information xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. For example, in the case of current sensing or voltage detection, assuming that the sense current value is defined as IS, the resistance value of the TMR element used for a cell is defined as R, and the magnetoresistance change ratio is defined as MR, VF and VAF can be obtained as follows.
VF=R(1xe2x88x92MR/2)xc3x97Isxe2x80x83xe2x80x83(1) 
VAF=R(1xe2x88x92MR/2)xc3x97Isxe2x80x83xe2x80x83(2) 
Assuming that the reference voltage is defined as an intermediate voltage between VF and VAF, the differential voltage inputted to a sense amplifier is as follows.
Vsig=Rxc3x97MRxc3x97Is/2xe2x80x83xe2x80x83(3) 
A factor of 2 in the denominator is due to the reference voltage VREF is set to the intermediate voltage. In the case of voltage sensing and current detection, assuming that a bias voltage is defined as Vbias, and a detection load resistance is defined as RL, similarly, the following formulas can be obtained.
VF=Vbiasxc3x97RL/R(1xe2x88x92MR/2)xe2x80x83xe2x80x83(4) 
VAFVbiasxc3x97RL/[R(1+MR/2)]xe2x80x83xe2x80x83(5) 
Vsig=Vbiasxc3x97RL/Rxc3x97MR/2xe2x80x83xe2x80x83(6) 
In the deriving process of formula (6), the fact that MR 2 less than  less than 1 is considered.
Therefore, in the prior art, only half of the magnetoresistance ratio of the TMR element can be utilized.
In order to solve these problems, for example, there is a method of using a magnetic field during read out by employing a TMR element in which a ferromagnetic layer 1 and a ferromagnetic layer 2 are ferromagnetically or anti-ferromagnetically coupled with each other (for example, refer to U.S. Pat. No. 5,734,605). However, this method is not suitable to application to a hand held device because power consumption during readout increases.
In addition, there is disclosed a method of disposing selection transistors for two TMR elements, respectively, thereby configuring a memory cell (for example, refer to ISSCC 2000 Digest paper TA7.2). In this method, writing is performed while the magnetization directions of the recording layers of two TMR elements are always anti-parallel to each other. That is, there is employed complementary write-in in which a magnetization configuration of either of the elements enters an anti-parallel state, and the magnetization of the other one enters a parallel state. In this method, outputs of these two elements are differentially amplified, thereby eliminating noise in the same phase, and improving the S/N. However, there is a problem that a cell area increases, and the degree of integration is lowered because two selection transistors are employed for a cell.
As described above, a TMR element is applied to a memory cell, whereby reduction of the sense current during readout and an increase in the cell output signal can be achieved at the same time, making it possible to provide an MRAM with its higher density than an MRAM using a conventionally employed GMR effect. However, even in the case where the TMR element is used for a memory cell, the cell output voltage is about some tens mV. In view of the magnitude of noise caused by dispersion in characteristics of semiconductor elements for driving a sense line or selecting a cell or the magnitude of noise from a data line and a periphery circuit, a sufficient signal-to-noise ratio is not obtained currently. In order to improve the signal-to-noise ratio, there is proposed a method using a magnetic field; and however, there is a disadvantage that power consumption during readout increases.
It is an object of the present invention to provide a magnetic memory device capable of increasing a cell output voltage during readout, and capable of improving a signal-to-noise ratio without causing an increase in power consumption during readout, the magnetic memory device being compatible with low power consumption and fast reading properties.
According to the present invention, there is provided a magnetic memory cell device comprising a plurality of tunnel junction sections that stack a pinned layer having its magnetization direction pinned therein and a recording layer having its magnetization direction changed by an external magnetic filed, and that configures single or double and more tunnel junction, wherein a memory cell that is an information recording unit is composed of two tunnel junction sections (first and second TMR elements), a first end in the stack direction of each of the first and second TMR elements is connected to each of the data lines, and a second end is connected to a bit line via the same cell selection semiconductor element.
In addition, according to the present invention, there is provided a magnetic memory cell device comprising a plurality of tunnel junction sections that stack a pinned layer having its magnetization direction pinned therein and a recording layer having its magnetization direction changed by an external magnetic filed, and that configures single or multi tunnel junctions, wherein the magnetic memory cell array is divided in a plurality of divided cell arrays, each divided cell array is made of first and second data lines disposed in parallel to each other, a plurality of word lines crossing these data lines, a bit line running in parallel to the data lines, and a plurality of magnetic memory cells. The magnetic memory cell is composed of two tunnel junction sections (first and second TMR elements), the first ends of the first and second TMR elements in the stack direction are connected to the first and second data lines, respectively, and the second ends are connected to the same bit line via the same cell selection semiconductor element.
Furthermore, according to the present invention, there is provided a magnetic memory cell device comprising a plurality of tunnel junction sections that stack a pinned layer having its magnetization direction pinned therein and a recording layer having its magnetization direction changed by an external magnetic filed, and that configures single or double and more tunnel junctions, wherein the magnetic memory cell array is divided in a plurality of divided cell arrays, each divided cell array being made of first and second subsidiary data lines disposed in parallel to each other, a plurality of word lines crossing these subsidiary data lines, a subsidiary bit line running in parallel to the subsidiary data lines, and a plurality of magnetic memory cells. The magnetic memory cell is composed of two tunnel junction sections (first and second TMR elements). The first ends of the first and second TMR elements in the stack direction are connected to the first and second subsidiary data lines, respectively. The second ends are connected to the same subsidiary bit line via the same cell selection semiconductor element. The first and second subsidiary data lines and a subsidiary bit line are connected to the first and second data lines and the bit line via a selection transistor, respectively.
Desired embodiments of the present invention are exemplified as follows.
(1) The resistance values and the magnetoresistance ratio of the first and second tunnel junction sections are substantially equal to each other, and the magnetization configuration of the both recoding layers of the tunnel junction sections is always in anti-parallel.
(2) One end of each of the first and second TMR elements is connected to each of the first and second data lines, and the other end is connected to a bit line via the cell selection semiconductor element.
(3) The stored information is read by comparing the magnitude of currents that flow the first and second data lines when a potential difference is applied between the first and second data lines and the bit line. In addition, the first and second data lines are kept at equal potentials.
(4) The stored information is read by comparing the magnitude of a voltage that appears in a bit line when a potential difference is applied between the first and second data lines.
(5) A first write line is disposed at one end in the stacking direction of the first TMR element, and a second write line is disposed at one end in the stacking direction of the second TMR element. Common write lines are disposed at the first or second end of the first TMR element in the stacking direction and at the first or second end of the second TMR element in the stacking direction. These common write lines are configured so as to be diagonal to the direction in which a current flows the first write line and the direction in which a current flows the second write line.
(6) The first and second TMR elements are disposed in the same plane. The first and second write lines are disposed in parallel to each other in the same plane. A third write line and the first and second write lines are in another plane, and are disposed so as to cross each other in the vicinity of the first and second TMR elements. Each of the first and second write lines is connected to the outside of a memory cell array region at one end.
(7) The first and second TMR elements are arranged in vertical direction, and the first and second write lines are disposed in parallel to the vertical direction. The third write line and the first and second write lines are disposed in parallel to each other in vertical direction in a plane. The third write line and the first and second write lines are in another plane, and are disposed so as to cross each other in the vicinity of the first and second TMR elements. Each of the first and second write lines is connected to the outside of a memory cell array region at one end.
(8) A cell selection semiconductor element is a MOS type field effect transistor, a diode element using a MOS type field effect transistor or a junction type diode element that employs pn junction or Schottky junction.
(9) The number of memory cells included in one subsidiary cell array is 1000 or less.
In the above arranged magnetic memory device, a method of reading stored information relevant to a memory cell first includes: activating a cell selection semiconductor element in a low impedance state during readout; and comparing the magnitude of currents that flows the first and second data lines when a potential difference is applied between the first and second data lines and the bit line. The first and second data lines are controlled so as to be the same potential. In this manner, the senses currents that depend on the potential difference and the resistance value of each TMR element flows the first and second data lines. The resistance values of the TMR elements are different from each other depending on whether a relative angle in magnetization between the pinned layer and the storage layer of the TMR element is parallel to or is anti-parallel to another.
In the magnetic memory device according to the present invention, the resistance values and magnetoresistance ratio of the two TMR elements are equal to each other, and the magnetization directions of the respective recording layers are anti-parallel to each other. Therefore, assuming that the potential difference is defined as Vbias, the resistance value of the first TMR element is defined as R (1xe2x88x92MR/2), and the resistance value of the second TMR element is defined as R (1+MR/2), the values I1 and I2 of the sense currents that flow the first and second data lines are as follows.
I1=Vbias/R(1xe2x88x92MR/2)xe2x80x83xe2x80x83(7) 
I2=Vbias/R(1+MR/2)xe2x80x83xe2x80x83(8) 
That is, a sense current difference Isig is obtained by Isig=V/Rxc3x97MR, where a greater differential signal than that of the prior art can be obtained. A memory cell is a current driven element. Thus, if there occurs a dispersion in resistance when a cell selection semiconductor connected to the TMR element in serial, the result is a dispersion in output signals. In the present invention, the first and second TMR elements share the same cell selection semiconductor element, thus making it possible to completely eliminate a dispersion caused by dispersion in characteristics of the semiconductor element. This is a great advantage that the prior art does not have.
In addition, the above reading method secondly include: activating a cell selection semiconductor element in a low impedance state during readout; and comparing the magnitude of a voltage that appears in the bit line when the potential difference is applied between the first and second data lines. Assuming that the potential difference between the first and second data lines is defined as Vbias, the resistance value of the first TMR element is defined as R (1xe2x88x92MR/2), the resistance value of the second TMR element is defined as R (1+MR/2), a potential difference V between the second data line and the bit line is obtained as follows.
V=Vbias/2xc3x97(1+MR/2)xe2x80x83xe2x80x83(9) 
Therefore, when the reference voltage VREF is set to:
VREF=Vbias/2xe2x80x83xe2x80x83(10) 
the signal voltage Vsig is obtained as follows.
Vsig=Vbias/2xc3x97MR/2xe2x80x83xe2x80x83(11) 
In this reading method, although the change of the signal voltage is smaller than that in the first reading method because a reference voltage is used, the following advantageous effects are provided.
(1) The differential voltage is no dependence on a current value that flows a TMR element. That is, even in the case where the number of memory cells in a memory cell array changes, and then, an impedance between a data line changes, the output is not affected.
(2) A bias voltage is divided by two TMR elements, and thus, the reduction of the magnetoresistance ratio depending on the applied voltage can be mitigate.
(3) Almost no current flows a bit line, and thus, dispersion in characteristics of the selection semiconductor element can be eliminated.
In the magnetic memory device according to the present invention, storage information is written into a memory cell by supplying a current to the first, second, and third write lines. In this duration, the value of a magnetic field is set so as to exceed that of the switching field of the TMR element only in a cross region for the first, second, and third write lines, whereby cell selection during write can be achieved.
In the magnetic memory device according to the present invention, the direction of a current that flows the first write line disposed at the first TMR element is opposite to the direction of a current that flows the second write line disposed at the second TMR element. That is, in the magnetic memory device according to the present invention, the magnetization directions of the recording layers of the first and second TMR elements that configure memory cells during write operation are always anti-parallel to each other. The information xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are discriminated depending on whether a relative angle of magnetization between a pinned layer of the element and a storage layer is parallel or is anti-parallel relevant to the first TMR element.
According to the invention, there is provided a magnetic memory device comprising a tunnel junction section including a magnetic memory layer formed of a stack of a first pinned layer having the magnetization direction pinned therein, a first tunnel barrier adjacent to the first pinned layer, a first magnetic layer which is opposite to the first pinned layer via the first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to the first magnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between the first and second magnetic layers, for anti-ferromagnetically coupling between the first and second magnetic layers, a second tunnel barrier adjacent to the second magnetic layer, and a second pinned layer opposite to the second magnetic layer via the second tunnel barrier, and a detection section configured to detect a current difference between a first tunnel current flowing across the first magnetic layer and the first pinned layer and a second tunnel current flowing across the second magnetic layer and the second pinned layer or a voltage difference in a differential scheme.
According to the invention, there is provided a magnetic memory device comprising a tunnel junction section including: a magnetic memory layer formed of a stack of a first pinned layer having the magnetization direction pinned therein, a first tunnel barrier adjacent to the first pinned layer, a first magnetic layer which is opposite to the first pinned layer via the first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to the first magnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between the first and second magnetic layers, for anti-ferromagnetically coupling between the first and second magnetic layers, a second tunnel barrier adjacent to the second magnetic layer, and a second pinned layer opposite to the second magnetic layer via the second tunnel barrier, a bit line electrically connected to all or either of the first magnetic layer, non-magnetic conductive layer, and second magnetic layer, a first data line electrically connected to the first pinned layer, and a second data line electrically connected to the second pinned layer.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.